/*
 * WonderSwan hardware definitions
 */

#define CPU_VEC_DIVIDE_ERROR 0
#define CPU_VEC_SINGLE_STEP 1
#define CPU_VEC_NMI 2
#define CPU_VEC_BREAKPOINT 3
#define CPU_VEC_OVERFLOW 4
#define CPU_VEC_ARRAY_BOUNDS 5

#define CPU_VEC_UART_TX 8
#define CPU_VEC_KEY_PRESS 9
#define CPU_VEC_CARTRIDGE 10
#define CPU_VEC_UART_RX 11
#define CPU_VEC_LINE_MATCH 12
#define CPU_VEC_VBLANK_TIMER 13
#define CPU_VEC_VBLANK 14
#define CPU_VEC_HBLANK_TIMER 15

#define IRQ_VECTOR_PORT 0xB0
#define IRQ_ENABLE_PORT 0xB2
#define IRQ_STATUS_PORT 0xB4
#define IRQ_ACK_PORT    0xB6

#define SYS_CONTROL_PORT 0xA0
#define SYS_CONTROL_IS_COLOR 0x02

#define TMR_CONTROL_PORT 0xA2
#define HBL_TMR_REPEAT 0x03
#define HBL_TMR_ONESHOT 0x01
#define VBL_TMR_REPEAT 0x0C
#define VBL_TMR_ONESHOT 0x04
#define HBL_TMR_RELOAD_PORT 0xA4
#define VBL_TMR_RELOAD_PORT 0xA6
#define HBL_TMR_COUNTER_PORT 0xA8
#define VBL_TMR_COUNTER_PORT 0xAA

#define UART_DATA_PORT 0xB1
#define UART_CONTROL_PORT 0xB3
#define UART_ENABLE 0x80
#define UART_B38400 0x40
#define UART_B9600  0x00
#define UART_OVR_RESET 0x20
#define UART_TX_READY 0x04
#define UART_OVR 0x02
#define UART_RX_READY 0x01

#define SCR_CONTROL_PORT 0x00
#define SCR_BASE_PORT 0x07
#define SCR1_SCROLL_PORT 0x10
#define SCR2_SCROLL_PORT 0x12

#define AUD_BASE_PORT 0x8F
#define AUD_CH1_FREQ_PORT 0x80
#define AUD_CH1_VOL_PORT 0x88
#define AUD_CONTROL_PORT 0x90
#define AUD_OUTPUT_PORT 0x91
